This invention relates to systems and methods for ion implantation of a workpiece and, more particularly, to methods and apparatus for ion implantation of semiconductor wafers with low energy ions.
Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material to form a region of desired conductivity.
Ion implantation systems usually include an ion source for converting a gas or solid material into a well-defined ion beam. The ion beam is mass analyzed to eliminate undesired ion species, is accelerated to a desired energy and is directed onto a target plane. The beam is distributed over the target area by beam scanning, by target movement or by a combination of beam scanning and target movement. Examples of prior art ion implanters are disclosed in U.S. Pat. No. 4,276,477 issued Jun. 30, 1981 Enge; U.S. Pat. No. 4,283,631 issued Aug. 11, 1981 to Turner; U.S. Pat. No. 4,899,059 issued Feb. 6, 1990 to Freytsis et al; and U.S. Pat. No. 4,922,106 issued May 1, 1990 Berrian et al.
A well-known trend in the semiconductor industry is toward smaller, higher speed devices. In particular, both the lateral dimensions and the depths of features in semiconductor devices are decreasing. State of the art semiconductor devices require junction depths less than 1000 angstroms and may eventually require junction depths on the order of 200 angstroms or less.
The implanted depth of the dopant material is determined, at least in part, by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies. Ion implanters are typically designed for efficient operation at relatively high implant energies, for example in the range of 50 keV to 400 keV, and may not function efficiently at the energies required for shallow junction implantation. At low implant energies, such as energies of 2 keV and lower, the current delivered to the wafer is much lower than desired and in some cases may be near zero. As a result, extremely long implant times are required to achieve a specified dose, and throughput is adversely affected. Such reduction in throughput increases fabrication cost and is unacceptable to semiconductor device manufacturers.
In one prior art approach to low energy ion implantation, the ion implanter is operated in a drift mode with the accelerator turned off. Ions are extracted from the ion source at low voltage and simply drift from the ion source to the target semiconductor wafer. However, a small ion current is delivered to the wafer because the ion source operates inefficiently at low extraction voltages. In addition, the ion beam expands as it is transported through the ion implanter, and ions may strike components of the ion implanter rather than the target semiconductor wafer.
Another prior art approach utilizes a deceleration electrode in the vicinity of the semiconductor wafer. Ions are extracted from the ion source at a higher voltage and then are decelerated by the deceleration electrode before being implanted into the wafer. This approach also suffers from ion beam expansion, such that only a small fraction of the ions generated by the source are incident on the target semiconductor wafer.
Accordingly, there is a need for improved methods and apparatus for low energy ion implantation.
According to a first aspect of the invention, an ion implanter is provided. The ion implanter comprises an ion beam generator including an ion source for generating ions and an extraction electrode having an extraction voltage applied thereto for accelerating the ions to form an ion beam, a holder for supporting a workpiece in the ion beam and a voltage generating circuit electrically connected to the workpiece. The voltage generating circuit applies to the workpiece a bias voltage that is of opposite polarity and smaller magnitude than the extraction voltage. The ions in the ion beam are implanted in the workpiece with an energy that is a function of the difference between the extraction voltage and the bias voltage.
The holder is preferably configured for supporting one or more semiconductor wafers. In one example, the holder comprises a disk for supporting a plurality of semiconductor wafers and a motor for spinning the disk so that the semiconductor wafers pass through the ion beam. The wafers may be in electrical contact with the disk. The ion implanter may further comprise dose electronics for measuring the dose of ions implanted in the wafers. The voltage generating circuit may comprise a power supply connected between the disk and the dose electronics. The bias voltage is typically in the range of about 0 to 2 kilovolts.
The ion implanter may further comprise a Faraday system positioned in front of the semiconductor wafer and means for biasing the Faraday system at the bias voltage. A plasma flood gun may be mounted in the Faraday system.
According to another aspect of the invention, a method for low energy ion implantation is provided. The method comprises the steps of generating ions in a source, accelerating the ions with a first voltage to form an ion beam, positioning a workpiece in the ion beam, and decelerating the ions in the ion beam by applying to the workpiece a second voltage that is of opposite polarity and smaller magnitude than the first voltage. The ions in the ion beam are implanted in the workpiece with an energy that is a function of the difference between the first and second voltages.